ATMEGA328P-15AZ【PDF 47/83 页】MCU AVR 32K FLASH 15MHZ 32-TQFP

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7810C–AVR–10/12

Atmel ATmega328P [Preliminary]

7.6.3

EECR – The EEPROM Control Register

Bits 7..6 – Res: Reserved Bits

These bits are reserved bits in the ATmega328P and will always read as zero.

Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits

The EEPROM Programming mode bit setting defines which programming action that will be trig-

gered when writing EEPE. It is possible to program data in one atomic operation (erase the old

value and program the new value) or to split the Erase and Write operations in two different

operations. The Programming times for the different modes are shown in Table 7-1. While EEPE

is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00

unless the EEPROM is busy programming.

Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing

EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-

rupt when EEPE is cleared. The interrupt will not be generated during EEPROM write or SPM.

Bit 2 – EEMPE: EEPROM Master Write Enable

The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written.

When EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM at the

selected address If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been

written to one by software, hardware clears the bit to zero after four clock cycles. See the

description of the EEPE bit for an EEPROM write procedure.

Bit 1 – EEPE: EEPROM Write Enable

The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address

and data are correctly set up, the EEPE bit must be written to one to write the value into the

EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, other-

wise no EEPROM write takes place. The following procedure should be followed when writing

the EEPROM (the order of steps 3 and 4 is not essential):

Wait until EEPE becomes zero.

Wait until SELFPRGEN in SPMCSR becomes zero.

Write new EEPROM address to EEAR (optional).

Write new EEPROM data to EEDR (optional).

Bit

7654

0x1F (0x3F)

–

EEPM1

EEPM0

EERIE

EEMPE

EEPE

EERE

EECR

Read/Write

R/W

Initial Value

Table 7-1.

EEPROM Mode Bits

EEPM1

EEPM0

Programming

Time

Operation

3.4 ms

Erase and Write in one operation (Atomic Operation)

1.8 ms

Erase Only

1.8 ms

Write Only

–

Reserved for future use

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